What They Say
IBM said that it has developed a chip with 2nm features that would improve performance by 45% over current 7nm chips and reduce power consumption by 75%. That would allow battery life for smartphones of up to four days.
The chip can put 50 billion transistors into “a chip the size of a fingernail” and was built at its Albany research lab. The architecture has been described as at three stack GAA or ‘Gate All Around’ design.
What We Think
It shouldn’t after all this time, but the development of chips still astounds me. I remember being in a research lab in 1971 when someone showed me a quad schmitt trigger IC. It had 8 transistors in and I was really impressed! At Anandtech.com I found this useful chart that helps to show the different density of the different makers.
The real implication for display makers is that a drop in the consumption of APUs might reduce the pressure to trim display power budgets. (BR)
IBM’s 3-stack GAA uses a cell height of 75 nm, a cell width of 40 nm, and the individual nanosheets are 5nm in height, separated from each other by 5 nm. The 2nm is ‘2D equivalent’ rather than the actual feature size.
