The continuing expansion of display performance requirements in mobile applications demands that a hybrid of software and hardware solutions come together to address the bandwidth requirements. Rambus is offering a platform to get to those every higher refresh rates and resolutions.
Rambus MIPI DSI-2, VESA DSC, VDC-M IP solutions help designers manage the bandwidth requirements of next-generation displays with extremely high resolutions and fast refresh rates. Combining both MIPI DSI and VESA video compression expertise, the IP cores are optimized for maximum performance and offer a mature IP solution to speed up the product development cycle and lower design risk.
Semiconductor Engineering
The MIPI Alliance is an international organization defining interface specifications that are suitable for mobile, AR/VR, and automotive displays applications. It’s MIPI Display Serial Interface 2 (MIPI DSI-2) specifies the high-bandwidth link between host processors and displays to deliver ultra-high-definition (UHD) video with low power consumption, less complexity and, hopefully, reduced costs. In reality, the physical layer of a device is a limiting factor, as you would expect, with premium smartphone designs hitting 120 Hz refresh rates and wanting to support 4K video.
Rambus has Hardent’s VESA DSC encoding with its own DSI-2 controller, and licensing Mixel’s IP cores for C/Phy-D/Phy for the physical connectivity layer. The combination of hardwired compression algorithms and Rambus’ already memory performance reduces the overall demands on the physical layer requirements. Mixel is providing the actual integrated solution but the three IP cores can also be licenses individually from each supplier.
Source: Hardent
Mixel’s MIPI C-PHY/D-PHY combo IP is a high-frequency, low-power, low-cost, physical layer. It can be configured as a MIPI transmitter or receiver, supporting both the camera interface MIPI CSI-2 v3.0 and display interface DSI-2 v1.1 and is backward compatible with previous generations of each specification. In C-PHY mode, Mixel’s MIPI C-PHY v2.0 supports a speed of 4.5 giga-symbols per second (Gsps) per trio which is an equivalent data rate of 10.26 Gbps/trio. In D-PHY mode, the IP supports speeds up to 4.5 Gbps per lane and complies with the MIPI D-PHY v2.5 specification. With up to three trios in C-PHY and up to four lanes in the D-PHY, the combo IP reaches an aggregate bandwidth of 30.78 Gbps and 18 Gbps in their respective modes.
The Rambus DSI-2 Controller cores are DSI-2 v1.1 compliant and optimized for high performance, low power and small size. The cores are full featured supporting host (Tx) and peripheral (Rx), multiple user interface options, and are highly configurable. 64 and 32-bit core widths are available enabling the user to make clock rate versus size tradeoffs.
MIPI DSI-2 supports both VESA DSC and VDC-M compression codecs. From the table below, we can see how effectively the bandwidth requirements can be mitigated with the use of compression codecs in hardware although there is still some room left for performance at the very high end, where greater bandwidth is require for AR and VR headsets.
MIPI has been around for twenty years. Rambus, Hardent and Mixel have been pushing their solution for at least 2 years. There’s a lot of good IP to leverage here, fortunately it is more a buffet service than a fix price meal, but it seems like there is a more pushing of to be done to get greater adoption.
