VESA has published the next version of the Embedded DisplayPort (eDP) standard: V1.4b. This takes eDP 1.4 to production-ready status.
The new version features several key protocol refinements and clarifications, resulting from VESA member companies’ product development efforts. The enhancements are intended to further optimise interoperability and time to market, for makers of integrated displays and personal electronic devices.
“From the onset, the development of eDP 1.4 has been all about power optimisation”, said Craig Wiley, senior director of marketing at Parade Technologies and editor of the DisplayPort 1.4 Standard. “Prior to eDP 1.4, eDP provided the highest performance and most optimized hardware interconnect, but not the lowest-power display interface for a given display resolution… eDP 1.4 puts eDP on parity with any other embedded interface regarding power consumption. Even with its added complexity, eDP is now more attractive even to the smallest devices because of its advantages. Along with our OEM partners, Parade believes that the eDP 1.4b release now represents the final eDP 1.4 implementation, and is now introducing Tcon products based on this standard”.
Like eDP 1.4a, eDP 1.4b specifies four high-speed HBR3 lanes between the graphics adapter and display; each operates at 8.1Gbps. These lanes can be divided between two or four independent panel segments, or used together for a theoretical total bandwidth of 25.92Gbps. A change to the original standard is an addition made to the Selective Update protocol for Panel Self Refresh. When sending the sub-frame video block for the partial update region, the Selective Update command from the video source now includes the Y-axis coordinate (line number) of where the region begins, instead of just the X-axis coordinate. Because this requires less precision in the asynchronous time base of the sink device, there is no need to include a discrete quartz crystal or crystal oscillator, as required by eDP 1.4. VESA writes that this lowers the system bill of materials cost.
The granularity of the X- and Y-axis of the selective update region has also been reduced. This can lower the complexity of the display’s remote frame buffer implementation. The effect is simplification of the internal video compression implementation.
Other refinements were made to the Selective Update protocol; the Multi-SST Operation feature; and the use of Display Stream Compression, Advanced Line Power Management and the auxiliary channel-based frame synchronisation.
It is thought that systems incorporating eDP 1.4b will be built by mid-2016.
