This month, a scientific paper entitled "Sub-10 nm Carbon Nanotube Transistor" was published in Nano Letters. In it, a research team headed by Aaron D. Franklin of the IBM T. J. Watson Research Center (Yorktown Heights, New York) report the first experimental evidence of a material capable of producing transistors sized below 10 nanometers, the theoretical limit for silicon based devices.

First, a few words of background.

The size of current Silicon Metal-Oxide-Semiconductor Field-Effect Transistor (Si MOS-FET) architectures is approaching 22 nm. There is, however, a real incentive to develop even smaller devices. A smaller architecture could not only enable the ability to reduce chip size and thus, reduce cost, but also to produce devices that consume less power. Silicon semicnductor manufacturers are particularly motivated to reduce feature size to gain additional years of use from their vast manufacturing infrastructure.

With these goals in mind, a recent Intel presentation stated that the company could have 10 nm chips ready by 2015. This may be accomplished by successfully achieving advances in the company’s so-called silicon-based 3D tri-gate FinFET approach.

Unfortunately, if the size of a silicon-based transistor is reduced to less than 10 nm, it begins to lose the ability to effectively control electric current. The problem is called "short-channel effects."

So, the question is: once the 10 nm limit is reached, what’s next?

One approach that researchers have been exploring are designs based on the use of hollow, cylindrically shaped single-walled Carbon NanoTubes (CNTs). CNTs have long been recognized as having great potential as a semiconductor material due to their superior electrical properties and ultra thin (1-2 nm diameter) bodies.

The experiments reported in this month’s paper were undertaken to test the theoretical performance of CNT transistors. This task was needed because, until the IBM researchers fabricated and tested sub-10 nm CNT transistors, it was uncertain how well they would perform. Part of the reason for concern derived from the fact that theories predicted that CNTs with ultra thin channels would also experience a loss of gate control as well as a loss of drain current saturation in the output. Both effects would degrade performance.

The good news is that the IBM researchers report that CNT transistors under 10 nm exhibited an impressively small inverse subthreshold slope of 94 mV/decade - nearly half the value predicted by a previous theoretical study. At 2.41 mA/?m, the CNTs also carried more than four times the diameter-normalized current density of the best competing silicon devices…and they did so at an operating voltage of 0.5, which is lower than silicon’s threshold. The improved current flow should result in improved signal quality.

The researchers fabricated the CNT transistors by laying a nanotube on a thin layer of insulation. A two-step process was then used to add the electrical gates.

Part of the results of the work to date was identification of problems that need to be addressed. These include:

• • A means to manufacture pure batches of semiconducting nanotubes. Any metal in the carbon mix will cause the transistor to short circuit.
• • A means to reliably obtain precise alignment in the placement of the CNT since this is required to form complex circuits having proper functionality.
• • Numerical simulations have shown the critical role of the metal-CNT contacts in determining the performance of sub-10 nm channel length transistors. This indicates the need for more accurate theoretical modeling of transport between the metal and the nanotube.

The superior low voltage performance of sub-10 nm CNT-based transistors establishes their viability as a candidate for future, smaller devices. This is particularly true when the application is logic circuits. None-the-less, the future prospects for CNTs remain uncertain.

Although IBM has made real progress in the development of CNT-based transistors, the technology is far from ready for commercialization. Add to this the fact that Intel is already going to market with products that use the company’s 3D tri-gate FinFET technology. These factors together could lead to a scenario in which there is enough time for the semiconductor industry to find a solution to the silicon leakage problem. This, in turn, would avoid the need for a change of material when it comes time to utilize sub-10 nm parts in commercial products. Time will tell. -Arthur Berman